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CY62136CV30/33 MoBL CY62136CV MoBL
2M (128K x 16) Static RAM
Features
* Very high speed: 55 ns and 70 ns * Voltage range: -- CY62136CV30: 2.7V-3.3V -- CY62136CV33: 3.0V-3.6V -- CY62136CV: 2.7V-3.6V * Pin-compatible with the CY62136V * Ultra-low active power -- Typical active current: 1.5 mA @ f = 1 MHz -- Typical active current: 5.5 mA @ f = fmax (70-ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered in a 48-ball FBGA This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
* * * * *
Functional Description[1]
The and CY62136CV are high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
128K x 16 RAM Array 2048 x 1024
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER BHE WE CE OE BLE
A12
A13
A11
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05199 Rev. *D
*
3901 North First Street
A14 A15 A16
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 20, 2002
CY62136CV30/33 MoBL CY62136CV MoBL
Pin Configuration[2, 3]
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 FBGA (Top View) 4 5 3 A0 A3 A5 NC A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
I/O12 DNU I/O13 NC A8 A14 A12 A9
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential -0.5V to VCCMAX + 0.5V DC Voltage Applied to Outputs in High-Z State[4] ....................................-0.5V to VCC + 0.3V DC Input Voltage[4] .................................-0.5V to VCC + 0.3V Output Current into Outputs (LOW) .............................20 mA
Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Device CY62136CV30 CY62136CV33 CY62136CV Range Ambient Temperature VCC 3.0V to 3.6V 2.7V to 3.6V
Industrial -40C to +85C 2.7V to 3.3V
Product Portfolio
Power Dissipation Operating, ICC (mA) VCC Range (V) Product CY62136CV30LL CY62136CV33LL CY62136CVLL VCC(min.) 2.7 3.0 2.7 VCC(typ.) 3.0 3.3 3.3
[5]
VCC(max.) 3.3 3.6 3.6
Speed (ns) 55 70 55 70 70
f = 1 MHz Typ.[5] 1.5 1.5 1.5 1.5 1.5 Max. 3 3 3 3 3
f = fmax Typ.[5] 7 5.5 7 5.5 5.5 Max. 15 12 15 12 12
Standby, ISB2 (A) Typ.[5] 2 5 5 Max. 10 15 15
Notes: 2. NC pins are not connected to the die. 3. E3 (DNU) can be left as NC or VSS to ensure proper application. 4. VIL(min.) = -2.0V for pulse durations less than 20 ns. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
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CY62136CV30/33 MoBL CY62136CV MoBL
Electrical Characteristics Over the Operating Range
CY62136CV30-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC = 3.3V IOUT = 0 mA CMOS Levels Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V 2.2 -0.3 -1 -1 7 1.5 2 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 15 3 10 2.2 -0.3 -1 -1 5.5 1.5 2 Typ.[5] Max. CY62136CV30-70 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 12 3 10 A Typ.[5] Max. Unit V V V V A A mA
VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz Automatic CE Power-down Current -- CMOS Inputs Automatic CE Power-down Current -- CMOS Inputs
ISB1
CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE, WE, BHE, and BLE) CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.3V
ISB2
CY62136CV33-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Test Conditions VCC = 3.0V VCC = 2.7V Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current --CMOS Inputs Automatic CE Power-down Current --CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.6V IOUT = 0 mA CMOS Levels IOL = 2.1 mA VCC = 3.0V VCC = 2.7V 2.2 -0.3 -1 -1 7 1.5 5 VCC + 0.3V 0.8 +1 +1 15 3 15 0.4 Min. 2.4 Typ.[5] Max. Output HIGH Voltage IOH = -1.0 mA
CY62136CV33-70 CY62136CV-70 Min. 2.4 2.4 0.4 0.4 2.2 -0.3 -1 -1 5.5 1.5 5 VCC + 0.3V 0.8 +1 +1 12 3 15 A Typ.[5] Max. Unit V V V V V V A A mA
ISB1
CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE, WE, BHE, and BLE) CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V
ISB2
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF
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CY62136CV30/33 MoBL CY62136CV MoBL
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[6] Thermal Resistance (Junction to Case)[6] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2
VCC Typ 10% GND Rise TIme: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
3.0V 1105 1550 645 1.75
3.3V 1216 1374 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[6] tR[7] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC= 1.5V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 1 Typ.[5] Max. Vccmax 6 Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes: 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
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CY62136CV30/33 MoBL CY62136CV MoBL
Switching Characteristics Over the Operating Range[8]
55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle[11] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BHE/BLE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[9, 10] 10 WE HIGH to Low-Z[9] 55 45 45 0 0 40 50 25 0 20 10 70 60 60 0 0 45 60 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[9] OE HIGH to High-Z CE HIGH to
[9, 10]
70 ns Max. Min. 70 55 70 10 55 25 70 35 5 20 25 10 20 25 0 55 25 70 35 5 20 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description
Min. 55 10
5 10 0
CE LOW to Low-Z[9] High-Z[9, 10] CE LOW to Power-up CE HIGH to Power-down BHE/BLE LOW to Data Valid BHE/BLE LOW to Low-Z[9]
5
BHE/BLE HIGH to High-Z[9, 10]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[12, 13]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. ItHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 12. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 13. WE is HIGH for read cycle.
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CY62136CV30/33 MoBL CY62136CV MoBL
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)
[13, 14]
ADDRESS
CE tACE OE
tRC tPD tHZCE
BHE/BLE
ttLZOE LZOE
tDOE
tHZOE
tHZBE
tDBE
tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
[11, 15, 16]
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Notes: 14. Address valid prior to or coincident with CE, BHE, BLE transition LOW. 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied.
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CY62136CV30/33 MoBL CY62136CV MoBL
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[11, 15, 16]
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Write Cycle No. 3 (WE Controlled, OE LOW)
[16]
tWC ADDRESS tSCE CE
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATAI/O NOTE 17 tHZWE DATAIN VALID
tHD
tLZWE
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CY62136CV30/33 MoBL CY62136CV MoBL
Switching Waveforms (continued)
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
ADDRESS
[16]
tWC
CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 17 DATAIN VALID tHD tBW tHA
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CY62136CV30/33 MoBL CY62136CV MoBL
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C)
Operating Current vs. Supply Voltage
14.0 12.0
14.0 12.0 ICC (mA) MoBL 8.0 6.0 4.0 2.0 (f = 1 MHz) 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) ICC (mA) 10.0 (f = fmax, 55 ns) (f = fmax, 70 ns)
10.0 8.0 6.0 4.0 (f = 1 MHz) 0.0 3.6 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 2.0 MoBL (f = fmax, 55 ns) (f = fmax, 70 ns)
Standby Current vs. Supply Voltage
12.0 12.0 ISB (A) 10.0 8.0 6.0 4.0 4.0 2.0 2.0 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 0 ISB (A) MoBL 10.0 8.0 6.0 MoBL
Access Time vs. Supply Voltage
60 MoBL
60 50 40 TAA (ns) 30 20 10 0
MoBL 50 40 TAA (ns) 30 20 10 0
2.7 3.0 3.3 SUPPLY VOLTAGE (V)
3.6 2.7 3.0 3.3 SUPPLY VOLTAGE (V)
Truth Table
CE H L L L L L WE X X H H H H OE X X L L L H BHE X H L H L L BLE X H L L H L Inputs/Outputs High-Z High-Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High-Z Data Out (I/O8-I/O15); I/O0-I/O7 in High-Z High-Z Mode Deselect/Power-down Output Disabled Read Read Read Output Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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CY62136CV30/33 MoBL CY62136CV MoBL
Truth Table (continued)
CE L L L L L WE H H L L L OE H H X X X BHE H L L H L BLE L H L L H Inputs/Outputs High-Z High-Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High-Z Data In (I/O8-I/O15); I/O0-I/O7 in High-Z Mode Output Disabled Output Disabled Write Write Write Power Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 70 Ordering Code CY62136CV30LL-70BAI CY62136CV30LL-70BVI CY62136CV33LL-70BAI CY62136CV33LL-70BVI CY62136CVLL-70BAI CY62136CVLL-70BVI 55 CY62136CV30LL-55BAI CY62136CV30LL-55BVI CY62136CV33LL-55BAI CY62136CV33LL-55BVI Voltage Range (V) 2.7-3.3 2.7-3.3 3.0-3.6 3.0-3.6 2.7-3.6 2.7-3.6 2.7-3.3 2.7-3.3 3.0-3.6 3.0-3.6 Package Name BA48A BV48A BA48A BV48A BA48A BV48A BA48A BV48A BA48A BV48A Package Type 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial
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CY62136CV30/33 MoBL CY62136CV MoBL
Package Diagrams
48-ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
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CY62136CV30/33 MoBL CY62136CV MoBL
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62136CV30/33 MoBL CY62136CV MoBL
Document History Page
Document Title: CY62136CV30/33/CY62136CV/CY62136CV30/33 2M (128K x 16) Static RAM Document Number: 38-05199 REV. ** *A *B *C ECN NO. 112379 114023 117063 118121 Issue Date 02/19/02 04/25/02 07/12/02 08/26/02 Orig. of Change GAV JUI MGN MGN Description of Change New Data Sheet (advance information) Added BV package diagram Changed Advance Information to Preliminary Changed Preliminary to Final Added new part numbers: CY62136CV with wider voltage (2.7V - 3.6V); CY62136CV33 narrower voltage range (3.0V - 3.6V) For TAA = 55 ns, improved tPWE Min from 45 ns to 40 ns For TAA = 70 ns, improved tPWE Min from 50 ns to 45 ns For TAA = 70 ns, improved tLZWE Min from 5 ns to 10 ns Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns) Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns) For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX + 0.5V Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC Input Voltage to VCC + 0.3V
*D
118622
10/3/02
MGN
Document #: 38-05199 Rev. *D
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